		FeedBack \| Contact Us \| Links \| Site Map

Welcome to Journal of Theoretical and Applied Information Technology

Submit Paper / Call for Papers

Journal receives papers in continuous flow and we will consider articles from a wide range of Information Technology disciplines encompassing the most basic research to the most innovative technologies. Please submit your papers electronically to our submission system at http://jatit.org/submit_paper.php in an MSWord, Pdf or compatible format so that they may be evaluated for publication in the upcoming issue. This journal uses a blinded review process; please remember to include all your personal identifiable information in the manuscript before submitting it for review, we will edit the necessary information at our side. Submissions to JATIT should be full research / review papers (properly indicated below main title).

Journal of Theoretical and Applied Information Technology March 2011 | Vol. 25. No.1

Paper ID:	1549 -JATIT
Title:	A NEW REACHABILITY BASED ALGORITHM FOR OUTLIER DETECTION IN MULTIDIMENSIONAL DATASET
Author:	K.SUBRAMANIAN, Dr. E. RAMARAJ
Source:	Journal of Theoretical and Applied Information Technology Vol 25. No. 1 -- 2011
Abstract	The quality of data is major role to detect novel results from the large voluminous databases. So the outlier detection is important process in KDD. It is another important area of data mining research. Maximum of the outlier are due to human errors. Many types of outlier detection algorithms are dealt with in the literature. This work also proposes a new algorithm for detection outliers. It uses new reachability based method for proposed algorithm. The efficiency of the proposed algorithm is proved by using core histogram, letter, segmentation, pima, breast datasets.
Keywords	Data Mining Quality Of Data Outlier Detection, Reachability, Multidimensional Dataset
Full Text

Paper ID:	14104 -JATIT
Title:	ARCHITECTURE FOR INTEGRATION OF POINT OF SALE TERMINALS WITH FINANCIAL INSTITUTIONS THROUGH WEB SERVICES
Author:	ERIK-JAN MONSHOUWER, RAUL VALVERDE
Source:	Journal of Theoretical and Applied Information Technology Vol 25. No. 1 -- 2011
Abstract	With the conventional POS payment transaction method, vendors are bound to a payment institute in their region and can only use relatively expensive dedicated or slow dial-up lines to their financial institute. This paper report covers the work to produce an architecture and a prototype that supports Point of Sales terminal payments over the Internet through web services. With the use of web services for payment transactions, vendors will get more freedom to choosing their provider and the services they take without having to throw away their legacy applications. Given the globalization of the economy, vendors can negotiate about services and fees with payment providers all over the world. Literature research and the prototype tests and evaluation in this project shows that transactions fees and performance of POS terminal payments transactions trough web services can be competitive to conventional payment transactions methods and create flexibility for vendors POS terminal application. Vendor’s available Internet connections and the web services standards in the market can be used for payment transactions. With web services the system can be created and changed relatively fast and simple if the right skills are available.
Keywords	POS, Architecture, FINANCIAL INSTITUTIONS, Vendors, Web Services., Transactions Fees
Full Text

Paper ID:	14107 -JATIT
Title:	OPTIMIZED TEST SCHEDULING WITH REDUCED WRAPPER CELL FOR EMBEDDED CORE TESTING
Author:	K. CHAKRAPANI, Dr. P. NEELAMEGAM
Source:	Journal of Theoretical and Applied Information Technology Vol 25. No. 1 -- 2011
Abstract	The increasing Design for Test (DfT) area overhead and potential performance degradation is caused due to wrapping all the embedded cores for modular System-on-Chip (SoC) testing. This paper proposes a solution for reducing the number of Wrapper Boundary Register (WBR) cells. By utilizing the WBRs of the surrounding cores to transfer test stimuli and responses, the WBRs of some cores can be removed without affecting the testability of the SoC. We denote the cores without WBRs as light-wrapped cores and present a new modular SoC test architecture for concurrently testing both the wrapped and the light-wrapped logic cores. Since the WBRs of cores that transfer test stimuli and test responses for light-wrapped cores become shared resources during test, conﬂicts arise during test scheduling that will negatively impact the test application time. The algorithm for SoC test scheduling and light-wrapped logic cores works under multiple constraints (test power dissipation, test resources and test priorities) and applies a Power Swarm optimization based optimum search for a solution to the scheduling problem. We consider the experiments on several SoC benchmark circuits and demonstrate that, with an acceptable increase in test application time, the number of WBRs can be signiﬁcantly decreased.
Keywords	System-on-Chip, Test Access Mechanism, Process Algebra, Fuzzy Logic
Full Text

Paper ID:	14122 -JATIT
Title:	TO MINIMIZE CURRENT DISTRIBUTION ERROR (CDE) IN PARALLEL OF NON IDENTIC DC-DC CONVERTERS USING ADAPTIVE NEURO FUZZY INFERENCE SYSTEM
Author:	B. SUPRIANTO, M. ASHARI, MAURIDHI H.P
Source:	Journal of Theoretical and Applied Information Technology Vol 25. No. 1 -- 2011
Abstract	A control system for non identical dc-dc converters using Adaptive Neuro Fuzzy Inference System (ANFIS) is presented. The converters are connected in parallel and have a non identical inductance value, L1≠L2≠L3, with 10% tolerance. The objective of control system is to balance the output current of each converter. One of converters is used as reference. The current error, which is subtraction of output current between the reference and other converters, is used as the ANFIS input. Therefore, it requires 2 ANFIS systems when 3 converters are in parallel. Each ANFIS has 5 membership functions. Simulations show that a system with 48 volt and various load resistances (from 10Ω to 0.75Ω) performs Current Distribution Error under 0.1%.
Keywords	Parallel dc-dc Converter, control methods, ANFIS
Full Text

Paper ID:	14129 -JATIT
Title:	CYCLICITY AND DECODING OF LINEAR ERROR-BLOCK CODES
Author:	RABII DARITI, EL MAMOUN SOUIDI
Source:	Journal of Theoretical and Applied Information Technology Vol 25. No. 1 -- 2011
Abstract	Linear error-block codes (LEBC) were introduced in [1]. They are a natural generalization of linear error correcting codes. In this paper, we introduce a notion of cyclic LEBC. In order to allow application in cryptography, especially in a McEliece-like cryptosystem [3], a method of decoding this kind of codes is presented. There exist linear error-block codes with fast decoding algorithms.
Keywords	Linear error-block codes, Cyclic and quasi-cyclic error-block codes, Decoding linear error-block codes
Full Text

Paper ID:	14138 -JATIT
Title:	BUSINESS CASES FOR ERP IMPLEMENTATIONS
Author:	Nora Al-Twairesh, Abdullah S. Al-Mudimigh
Source:	Journal of Theoretical and Applied Information Technology Vol 25. No. 1 -- 2011
Abstract	The rising expenses of information systems and their growing importance to organizations have made the justification of projects increasingly critical. The justification is usually done through a business case that is an initial step for organizations approaching an ERP implementation. The issue of developing a business case and using it during ERP implementations successfully is challenging and under-researched. This paper is a literature review on business cases in ERP, we try to identify the research issues that need to be addressed in this area and give some guidelines to developing a business case for ERP implementation.
Keywords	Business Case, ERP, Organization, integrity
Full Text

Paper ID:	14128 -JATIT
Title:	WIRELESS SENSOR NETWORK SIMULATION OF THE ENERGY CONSUMPTION BY A MULTI AGENTS SYSTEM
Author:	Rahal ROMADI, Hassan Berbia, B.Bounabat
Source:	Journal of Theoretical and Applied Information Technology Vol 25. No. 1 -- 2011
Abstract	A Wireless Sensor Network (WSN) is one that is in continual interaction with its environment, and executes at a pace determined by that environment. The use of rigorous formal method in specification and validation can help designers to limit the introduction of potentially faulty components during the construction of the system. Due to their complex nature, WSN are extremely difficult to specify and validate. In this paper, we propose a new formal model for the specification and the validation of such systems. This approach considers a WSN as a Reactive Multi-Agent System consisting of concurrent reactive agents that cooperate with each other to achieve the desired functionality. In addition, this approach uses formal synchronous specification and verification tools in order to specify and to verify the systems behaviors.
Keywords	Wireless Sensor Network, Reactive systems, Reactive agent, specification, formal methods, verification.
Full Text

Paper ID:	14116 -JATIT
Title:	AREA-TIME OPTIMAL VLSI INTEGER MULTIPLIER WITH MINIMUM COMPUTATIONAL TIME AND WEBER PROBLEM
Author:	Prof. M.THIYAGARAJAN, R. MANIKANDAN
Source:	Journal of Theoretical and Applied Information Technology Vol 25. No. 1 -- 2011
Abstract	The Ill-post problem on a VLSI Design namely area-time optimal VLSI Integer multiplier with minimum computation time can be regarded as a weber problem. The elementary results with extension leading to the classical problem on VLSI integer multiplier can be posed and settled in affirmative.
Keywords	VLSI, Multiplier, Extension, Computation Time
Full Text